In recent years, there has been an increasing demand for a semiconductor device including a MOSFET configured along side surfaces of trenches (hereinafter referred to as “trench semiconductor device”), because this semiconductor device has a lower ON resistance than a semiconductor device including a MOSFET (planar DMOSFET (double diffused MOSFET)) configured along an upper surface of an epitaxial layer.
A conventional trench semiconductor device is shown in FIG. 4. The semiconductor device 101 includes an N− type epitaxial layer 111 provided on an upper surface of an N type semiconductor substrate 110. A plurality of trenches (grooves) 120 are provided in the epitaxial layer 111 as extending downward from an upper surface of the epitaxial layer 111. A MOSFET is configured along opposite side surfaces of the trenches 120.
That is, a gate electrode 121 is embedded in each of the trenches, and an N+ type source region 113 and a P− type base region 114 are arranged in this order toward a lower side along each of the opposite side surfaces of the trenches 120. A portion of the epitaxial layer 111 below the base region 114 serves as an N− type drain region 115. A base high concentration region 116 is provided adjacent the source region 113 and the base region 114 in spaced relation from the trench 120 as extending downward from the upper surface of the epitaxial layer 111. The base high concentration region 116 has the same conductivity type as the base region 114 and a higher impurity concentration than the base region 114, and is shallower than the base region 114. The base high concentration region 116 has an ohmic contact with a source electrode 125 to be described later, and reduces the resistance component of the base region 114.
A gate insulating film 122 of a thin silicon oxide film is provided between the trench 120 and the gate electrode 121. The gate insulating film 122 extends onto the upper surface of the epitaxial layer 111. Further, an interlayer insulating film 123 is provided on the gate electrode and the gate insulating film 22 as partly covering the upper surface of the epitaxial layer 111. The gate insulating film 122 and the interlayer insulating film 123 each have an etched-off portion serving as a contact hole 124 on a part of the source region 113 and an upper surface of the base high concentration region 116. A metal layer is provided as the source electrode 125 to provide electrical contacts to the source region 113 and the base high concentration region 116 through the contact hole 124.
Where the semiconductor device 101 is in an OFF state, depletion layers 140 and 141 are formed as respectively spreading from lower surfaces of the base region 114 and the trench 120 into the drain region 115 in the epitaxial layer 111 as shown in FIG. 5. The depletion layer 140 spreading from the base region 114 has a relatively great width, while the depletion layer 141 spreading from the lower surface of the trench 120 has a relatively small width. A gate-drain capacitance CGD which is a capacitance between the gate electrode 121 and the drain region 115 is generally equal to a capacitance provided by serially coupling the capacitance of the gate insulating film 122 with the capacitance of the depletion layer 141 formed below the lower surface of the trench 120. The value of the capacitance of the depletion layer 141 is inversely proportional to the width of the depletion layer 141. Therefore, the depletion layer 141, if having a smaller width, has a greater capacitance value, resulting in a greater gate-drain capacitance CGD. Conversely, the depletion layer 141, if having a greater width, has a smaller capacitance value, resulting in a smaller gate-drain resistance CGD.    Patent Document 1: Japanese Unexamined Patent Publication No. 8-250731